The present disclosure relates to managing speculative load data in byte-write capable register file and history buffer utilized in a multi-slice microprocessor.
In traditional processors, load data is written into a general purpose register (GPR) when an address translation of a corresponding instruction is known. As such, data is typically not written into the general purpose register until the load instruction passes translation and the data is in a cache. However, in order to improve performance, load data may be returned and written into a general purpose register or history buffer before the address translation is known.
Traditional processor architectures typically structure an issue queue, register, and history buffer in a one-to-one configuration that receives writeback data in its entirety from a load store unit. As such, the issue queue, register, and/or history buffer store the writeback data in their corresponding entries that include instruction tag (ITAG) values matching the writeback data's ITAG values. However, processors with distributed architectures may configure issue queues, registers, history buffers, and load store units in a distributed manner instead of the one-to-one configuration as in traditional processor designs. As such, processors with a distributed architecture may have multiple load store units able to provide portions of the writeback data to the issue queue, register, and/or history buffer.